Archive for the ‘fab’ Category
Monday, August 17th, 2009
Luminescent Technologies, Inc., a computational lithography company, has broadened its reach by announcing the industry’s first offline computational photomask inspection product (unofficially named LAIPH for Luminescent Automated Image Processing Hub). A “premier company in Asia” is the first customer to qualify the new computational defect review product in volume production. According to a Luminescent representative, […]
Luminescent Inspection or LAIPH
Tags: 22nm, 32nm, 45nm, aerial, defect, IC, inspection, litho, mask
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Wednesday, August 12th, 2009
At the SEMICON West 2009 Device Scaling TechXPOT, moderated by this editor, SEMATECH’s Ray Jammy reviewed the latest results in scaling CMOS transistors. “We are litererally running out of atoms,” explained Jammy. “You can see the number of atoms in a gate dielectric.” When you have such thin layers, how do you control device parameters? […]
IC HK gate scaling limits
Tags: 22nm, 32nm, 45nm, ALD, dipole, fab, gate, HfO2, high-k, HKMG, IC, junction, R&D, RTP
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Tuesday, August 4th, 2009
While EUV Lithography may now be inevitable, according to SEMATECH Program Manager Bryan Rice, it may not be indispensable. SEMICON West offered a snapshot of progress towards the 32nm, 22nm, and 16nm device nodes at the Device Scaling TechXPOT, and the industry appears to have patterning options even if EUV encounters further delay. Yan Borodovsky […]
PS –We don’t need EUV!
Tags: 11nm, 16nm, 193i, 22nm, 7nm, EbDW, EUV, IC, ITRS, litho, NIL
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Thursday, July 30th, 2009
Evergreen Solar, the manufacturer of “String Ribbon” solar power products, announced it has finalized agreements with Jiawei Solarchina and the Wuhan government’s Hubei Science & Technology Investment Co., Ltd. (“HSTIC”) for the setup and operation of a new 100MW mc-Si panel fab. Factory construction has begun and the parties expect that wafer, cell, and panel […]
Wuhan provides US$33M for Evergreen/Jiawei 100MW PV line
Tags: fab, JV, mc-Si, PV, silicon, solar
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Wednesday, July 22nd, 2009
At SEMICON West and Intersolar North America last week in San Francisco, crossing guards danced to keep the throngs away from the vehicles at the corner of 4th and Howard, as many people flowed back and forth between the shows co-located across 4th Street from each other. SEMICON West, down ~30% in size from last […]
Intersolar and SEMICON in SF show fab tech marches on
Tags: 22nm, 32nm, IC, Material, OEM, PV, SEMI, Semiconductor
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Friday, July 10th, 2009
Intersolar North America 2009, co-located with SEMICON West in San Francisco next week, will include a Solar Startups Forum on July 16 to showcase some new technologies that are now in beta tests in the field. Select companies will make in depth presentations and offer insight into the atmosphere and environment of the solar industry […]
Successful Solar Startups to be shown
Tags: beta, CdTe, CPV, fab, PV, test, TW
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Tuesday, July 7th, 2009
Applied Materials has extended physical vapor deposition (PVD) technology to be able to coat the sidewalls of 22nm node structures. “It’s been validated, it’s been shipped, and it’s been qualified in pilot lines for both logic and memory,” asserted Marek Radko, Applied Materials’ BEOL GPM Manager, in an exclusive interview with BetaSights. Separately, the company […]
New PVD for both nano and micro
Tags: 22nm, 32nm, barrier, barrier/seed, Cu, damascene, fab, IC, metal, PVD, seed, TSV, UBM
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Friday, May 8th, 2009
Today, Intel sponsored a history of the planar IC event at the Computer History Museum, in Mountain View, California. This, in the same week that the company pre-launches a new advertising campaign to try to position the company as “Sponsors of Tomorrow.” Based on the live event, the past was seriously wonderful. Based on these […]
Intel – sponsors of yesterday
Tags: Al, bipolar, boron, diffusion, fab, IC, MOS, NPN, R&D
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Friday, May 1st, 2009
Leaving California for the first time, the 12th annual IEEE International Interconnect Technology Conference (IITC) will take place in Sapporo, Japan, June 1-3. With lithographic shrinks in 2D dimensions slowing, interconnects between chips in packages and in 3D stacks will be the driver for increased density and functionality in ICs. Thus, the more than 80 […]
IITC in Sapporo for 22nm interconnects and 3D
Tags: 22nm, 32nm, 3D, 45nm, 65nm, contact, Cu, dielectric, IC, integration, low-k, TSV, W
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Thursday, April 30th, 2009
Human intellectual development has eclipsed emotional development, with the resulting problem of clever people lacking morals. In government, industry, and academia there are endless examples of this problem, which is now threatening the economy due to corruption, and the very biosphere of the earth due to pollution. It is heartening that MIT (that trained most […]
MIT opens Dalai Lama center for ethics
Tags: ethics, PV, R&D
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