Intel shows vertical integration pays off with air-gaps through manufacturing cost reduction in low-k dielectrics for 32nm and 22nm node IC interconnects.

HP Labs in Palo Alto has been leading the development of the “memristor,” and researchers there have finally discovered the underlying mechanism for the formation of devices that can function as memory cells, logic circuits, and potentially even real artificial intelligence (AI)! Disclosing these results in his plenary speech to the attendees at the Nanocontacts […]

The 2010 SPIE Advanced Lithography conference is where we first get glimpses of the future of nano-scale patterning technology for manufacturing. Sometimes, many fuzzy blobs come into focus as a picture in a single moment, and Yan Borodovsky of Intel showed how to do 22nm node litho the day before SPIE officially started. At both […]

The upcoming Spring Materials Research Society (MRS) Meeting in San Francisco will feature a separate “Nanocontact and Nanointerconnects Workshop” to explore the biggest secret about the smallest devices: for the near-term there’s nothing better than standard metal. The workshop will address both theoretical and experimental approaches to formation, carrier transport, and reliability, and so will […]

Another back-to-the-future possibility for next-generation lithography (NGL) is direct write e-beam (DWEB), revitalized with multibeam clusters, curvilinear mask writing, and character projection (CP). The E-beam Initiative used the recent SPIE gathering to announce that it had added six new member companies, including GlobalFoundries and Samsung. Aki Fujimura, CEO of D2S and Managing Director of the […]

This year’s plenary sessions of the SPIE Advanced Lithography Symposium exposed the complexities of patterning ICs in high-volume manufacturing (HVM) at the 22nm node and beyond. Steppers using 193nm ArF immersion (193i) will be extended using double-patterning (DP) schemes, since the extreme-ultra-violet litho (EUVL) infrastructure is again delayed. R&D to support DP integration has led […]

Molecular Imprints, Inc, announced their first nanopatterning tool designed for pilot and volume production of patterned hard disc drive (HDD) substrates at the SPIE Advanced Lithography Symposium in San Jose, CA February 22. The NuTera HD7000 uses Jet and Flash Imprint Lithography (J-FIL) technology to print over 300 double sided disks per hour up to […]

The SPIE’s 7th Frits Zernike Award for Advances in Optical Microlithography goes to M. David Levenson, BetaSights Litho & DFM Editor, in recognition of one of the most important developments in lithography resolution enhancement of the last twenty years, the phase shifting mask (PSM). About 30 years ago at the IBM San Jose Lab, Levenson […]

The IEEE’s International Electron Devices Meeting (IEDM) is still the place to see the latest micro- and nano-electronics research targeting commercial markets. On December 8, 2009, French researchers from Leti/Minatec showed “3D sequential CMOS integration” as <600°C processing of PFETs using a (110) orientation FDSOI layer that was transferred on top of NFETs made using […]

Based on proven hardware sub-systems from previous models, Applied Materials has released a new chemical-mechanical planarization (CMP) tool that processes two 300mm diameter wafers simultaneously on each of two plattens. Initially targeting copper interconnect formation for memory ICs, the Reflexion GT tool has passed betasite tests at multiple customers, and reportedly provides 60% higher throughput […]