Xilinx 28nm FPGA Virtex-7 uses TSMC 65nm multi-level-metal (MLM) and through-silicon-via (TSV) Si-interposer for 2M gate and ARM-core integration product family.

IEDM 2010 best hints at 22nm node fab tech alternate-channel materials, dual- and tri-gate transistors, and RF, MEMS, lab-on-chip, graphene, analog, memory ReRAM results.

Direct-write, maskless, lithography using e-beams is not ready for 22nm node IC manufacturing, and the SPIE BACUS presentations show EbDW issues include data transfer and inspection.

TSV for 3D integration of heterogeneous ICs used in interposers first, as shown at SEMICON/West, IMAPS, IEDM and companies like ASE, Alchimer, Suss, EVG, Novellus, Vertical Circuits, and IBM.

E-beam Initiative adds four members and starts on Design for E-beam (DFEB) for mask makng for ICs to reduce mask costs at 22nm and below.

HP and Hynix JVA for ReRAM chips, based on HP titania memristor as covered by BetaSights April 2010, with R&D fab in Korea to start work on integration on 300mm silicon wafers for 2013 IC chips

For 32nm and 22nm node ICs, Applied Materials’ FCVD and Novellus Systems’ CFD technologies provide gapfill, sidewall spacers, and conformal oxides for logic and NAND, plus SSDP litho.

Post-optical lithography (NGL) technologies EUV (EUVL), e-beam direct-write (EbDW), and nano-imprint (NIL) all need work as shown at SEMICON/West 2010, major costs limitations.

SEMICON/West 2010 lithography changes were slight, TEL showed quadruple-patterning with ALD sidewall spacers and tools, Nikon and ASML with IMEC also showed double-patterning

Applied Materials kills the turnkey SunFab thin-film a-Si/mc-Si PV line, after failing to keep up with CdTe and CIGS thin-film technologies in efficiency and cost, taking ~$400M loss.