One year after this editor covered an SPIE panel on reference metrology and summarized the situation as “there is no more noise; there is only signal,” another lively panel at SPIE this evening discussed the need for not just precise but accurate critical dimension (CD) measurements in advanced IC lines. With smaller structures and reduced […]
Applied Materials’ Technical Symposium at SPIE 2009 featured a panel discussion on next generation lithography (NGL) that was moderated by the company’s Ken MacWIlliams. The outstanding panelists were C. Grant Willson (UT-Austin), Burn Lin (TSMC), Jongwook Kye (AMD), Steve Radigan (Sandisk), and Milind Weling (Cadence). As would be expected from this panel, EUV steppers were […]
At the Nikon Lithovisions 2009 Symposium on February 22 this year in San Jose, California, Masato Hamatani described the features and beta test results for the NSR-S620 scanning immersion exposure tool, optimized for double patterning lithography. While the tool boasts only one wafer stage, its “Streamlign Platform” concept shoots 200 wafers per hour with 2nm […]
JEOL will install the first e-beam direct-write-on-wafer (EBDW) lithography tool to support nanotechnology development in the Pacific Northwest when the University of Washington takes delivery of a JBX-6300FS tool. The system will be installed in the state-funded Washington Technology Center Microfabrication Lab. Funding for the tool acquisition was provided through a state-supported STAR researchers’ grant […]
As computational lithography has become big big business, the pioneering enterprises have been assimilated into larger organizations (KLA-Tencor for Finle and Synopsys for Sigma-C, to name two examples). Panoramic Technology, however, continues its independence, supplying trustworthy and up-to-date simulators to advanced lithographers for a decade. Past Panoramic products, however, employed an interface that was familiar […]
JSR announced today that it has entered into several joint development partnerships (JDP) with IBM to develop low-k dielectrics for 32nm and 22nm nodes of semiconductor technology. The companies will work on next generation materials JSR has had in development and commercial production, including low-k dielectrics and a broad range of photoresists. “This larger scale […]
For thick plating applications like copper pillar bump processing in semiconductor advanced packaging, Shin-Etsu MicroSi has introduced a positive tone, ultra-thick photoresist, SIPR-7126. The 7100 chemically amplified (CA) series has been in production for several years, and the SIPR-7126 has been optimized to reduce processing steps and improve removability in layers up to 100 µm […]
Metrosol has joined SEMATECH’s Front End Process Technologies Program at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany to address metrology and data-analysis solutions for 45nm node and beyond IC fabs. The joint partnership will expand on current work to develop inline metrology techniques to monitor the thickness and composition […]
Evident Technologies has announced the issuance of US Patent No. 7,482,059 covering the ability to synthesize a quantum dot with a metal layer which dramatically enhances the brightness and stability of a semiconductor nanocrystal complex. This advance of semiconductor materials science relies on a relatively low-cost colloidal formation processing, instead of needing epitaxial lattice-matching or […]
CaliSolar is ramping production of upgraded metallurgical-grade silicon (UMG-Si) solar cells and has selected Eyelit’s manufacturing software suite to support its new fab next to its headquarters in Sunnyvale, California. CaliSolar is a private company claiming 15% conversion efficiency from cell made using 100% UMG-Si feedstock that undergoes purification at both the ingot and wafer […]