Wednesday, February 4th, 2009
Allvia, the first through-silicon via (TSV) foundry, has secured $5 million from private investors in a round of funding to expand manufacturing facilities and to build more capacity. After 3 years of revenue generation from providing vertical interconnects and System-in-Package (SiP) solutions, total investment in the company is now $25 million. With in-house processing equipment, […]
Allvia TSV foundry adding capacity
Tags: 3D, foundry, IC, interconnect, MEMS, package, RF, Service, Si, TSV
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Friday, January 30th, 2009
Ziptronix wants to help you with your 3D roadmap. The IP spin-out from Research Triangle Park, NC is now actively negotiating licenses to its unique wafer-to-wafer (W2W) and die-to-wafer (D2W) bonding technologies. Using treated-oxide (with surface treatments) and nickel (with a mystery metal) as the connecting materials, room temperature bonding with up to 108/cm2 of […]
Ziptronix floats IP licenses for 3D IC bonding
Tags: 3D, bonding, IC, InP, integration, IP, Ni, oxide, Si, TSV
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Thursday, January 22nd, 2009
At SEMICON Korea 2009, SUSS MicroTec unveiled the second generation of its ACS300, a modular system for coating, baking and developing of wafers up to 300mm. Compared to the prior generation, the Gen2 tool reportedly costs less, has reduced footprint, and offers configuration flexibility with new capabilities. The system architecture and process modules are specifically […]
SUSS out with new 300mm track for 3DIC
Tags: 300mm, 3D, IC, lithography, OEM, packaging, tool, track
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Wednesday, January 14th, 2009
Smart Equipment Technology (S.E.T.), a wholly-owned subsidiary of Replisaurus Technologies and a leading supplier of high accuracy die-to-die (D2D), die-to-wafer (D2W) bonding and nanoimprint lithography solutions, announced yesterday that it will collaborate with IMEC on 3DIC R&D. IMEC’s 3D integration program explores 3D technology and design for applications in various domains, focusing on 3D WLP […]
Replisaurus 3DIC R&D with IMEC
Tags: 3D, bonder, chip, ECPR, flip-chip, IC, integration, interconnect, JDP, stacked
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Tuesday, January 13th, 2009
At SEMI’s Industry Strategy Symposium (ISS) running at Half Moon Bay, California today, IMEC president and CEO Gilbert Declerck talked about the need for R&D to facilitate IC industry growth. An industry based on answering the question, “what have you done for me lately?” can never rest on past successes and must continue to innovate. […]
ISS growth theme set by IMEC
Tags: 32nm, 3D, ADT, CMOS, EUV, fab, IC, investment, lithography, MEMS, Moore, R&D, SoC
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