Direct-write, maskless, lithography using e-beams is not ready for 22nm node IC manufacturing, and the SPIE BACUS presentations show EbDW issues include data transfer and inspection.

TSV for 3D integration of heterogeneous ICs used in interposers first, as shown at SEMICON/West, IMAPS, IEDM and companies like ASE, Alchimer, Suss, EVG, Novellus, Vertical Circuits, and IBM.

E-beam Initiative adds four members and starts on Design for E-beam (DFEB) for mask makng for ICs to reduce mask costs at 22nm and below.

HP and Hynix JVA for ReRAM chips, based on HP titania memristor as covered by BetaSights April 2010, with R&D fab in Korea to start work on integration on 300mm silicon wafers for 2013 IC chips

For 32nm and 22nm node ICs, Applied Materials’ FCVD and Novellus Systems’ CFD technologies provide gapfill, sidewall spacers, and conformal oxides for logic and NAND, plus SSDP litho.

Post-optical lithography (NGL) technologies EUV (EUVL), e-beam direct-write (EbDW), and nano-imprint (NIL) all need work as shown at SEMICON/West 2010, major costs limitations.

Soft plasmas for monolayer etching by Ed Korczynski at NCCAVS PAG meeting at SEMICON/West 2010, including TEL Tactras RLSA and AMAT AdvantEdge Mesa for HKMG 32nm, STI, and bWL etches.

ALD/CVD systems for new materials R&D by Altatech Semiconductor sold to Fraunhofer IZM ASSID and ENAS for 3DIC and high mobility research using liquid injection of precursors.

Intel shows vertical integration pays off with air-gaps through manufacturing cost reduction in low-k dielectrics for 32nm and 22nm node IC interconnects.

The upcoming Spring Materials Research Society (MRS) Meeting in San Francisco will feature a separate “Nanocontact and Nanointerconnects Workshop” to explore the biggest secret about the smallest devices: for the near-term there’s nothing better than standard metal. The workshop will address both theoretical and experimental approaches to formation, carrier transport, and reliability, and so will […]