James Quinn, CEO of Replisaurus, has been very busy executing for the last few years to bring his vision of a new metallization technology to the IC fab industry. Targeting the formation of Cu interconnects for advanced packaging applications, Quinn has assembled a great team to work with CEA-Leti and other industrial partners on a selective electro-chemical deposition (sECD) technology called electro-chemical pattern replication (ECPR).

Also known as patterned ECD, sECD has been explored for many years, with a recent failure in the form of the NuTool technology acquired and abandoned by ASM. Among the issues with prior attempts to develop a manufacturable sECD technology, electrical current non-uniformity across the wafer was inherent due to horizontal flux across templates. In contrast, Replisaurus uses a thick bus to shuttle current across the template, with dielectric isolation from the Cu pattern such that the current flux during ECD is essentially purely vertical.

The Replisaurus technology uses 15µm deep trenches filled with 10µm of Cu, and transfers only ~5µm per wafer pass (see figure), typically within one minute. The typical resolution is 5µm/5µm (line/space), though 500nm/300nm has been demonstrated. A reusable master electrode is used as a template to fabricate work-master patterns. The work-master provides pattern definition and metal deposition in one step, thus eliminating the need for traditional photolithography and plating. A single tool can thus replaces 6 tools in a typical though mask plating process (coat, expose, develop, descum, electroplate, and strip), reducing capital investment from 10-30M down to only 4-8M euros.

The template mastering has been established through a joint venture (JV) with Leti called Replisaurus Mastering, and the program is already up and running at Leti’s facility in Grenoble. “The mastering process is a central part of our business model and a unique component of our technology, so Leti’s practical, business-oriented approach to IP rights was a major factor in our decision to partner with them,” said James Quinn, CEO of Replisaurus. “We are moving forward according to plans to roll out our technology, and through this partnership Leti will support us in transferring it to a foundry partner.”

Since Leti has 8,000 m2 of state-of-the-art 200 mm and 300 mm wafer clean rooms, and 1,200 employees running in “24/7 mode,” the organization can easily supply the templates. Alan Cuthbertson, coming from senior management positions in Cu and low-k interconnect technology development for 130nm and 90nm node ICs, is Replisaurus’ vice president of Mastering Technology. “CEA-Leti has advanced capabilities with CMOS and MEMS applications that will be a great testbed for our technology as we look to apply it in other application areas,” said Cuthbertson. “We will focus on 200mm silicon and 300mm through this project and Leti’s world-class facility is the perfect place to enhance our technology for the chip market.”

Replisaurus also has established a “common laboratory agreement” with Leti. Under the multi-year agreement, Replisaurus and Leti personnel will collaborate on optimizing the development of reusable master electrodes. The two sides will also investigate the opportunities for this technology in new applications, notably in key growth sectors such as integrated passives, copper pillars, and 3D integration. The team will optimize electrode design and fabrication flow for each application area, ensuring the best yield, endurance, and cycle time.

“This new project with Replisaurus is a very exciting challenge as we help integrate its innovative clean metallization technology into a high-volume manufacturing solution. All of the necessary technical developments are already underway, and this collaboration got off to a great start,” said Laurent Malier, general manager of CEA-Leti. “In addition, access to ECPR technology through this agreement will enable Leti to position itself at the leading edge of research into advanced interconnect and device packaging technologies for diverse applications.”

Mike Thompson joined Replisaurus as COO last fall, after 17 years at STMicroelectronics Crolles, France, most recently as the deputy CTO of STMicroelectronics, with responsibility for CMOS R&D, covering design and process technology and the Crolles 200-mm and 300-mm operations. Prior to this, Thompson also helped establish ST’s participation to the IBM bulk CMOS Alliance and the Crolles2 Derivatives Technology Alliance in Crolles. –E.K.

Luminescent Technologies, Inc., a computational lithography company, has broadened its reach by announcing the industry’s first offline computational photomask inspection product (unofficially named LAIPH for Luminescent Automated Image Processing Hub). A “premier company in Asia” is the first customer to qualify the new computational defect review product in volume production. According to a Luminescent representative, revenue has changed hands, successfully ending the beta-test process.

During ordinary photomask inspection, operators manually sort through and evaluate defect images obtained using optical inspection and defect review tools to determine if anomalies on a photomask will affect wafer yield. This is time consuming, and subject to operator variability. Photomask customers have demanded that all identified defects be repaired, whether or not the inspector deems them printable or not.  Luminescent’s computational solution provides automated mask defect review and dispositioning based on aerial images of the photomask. The product accepts images from commonly used mask defect inspection and review tools, enhances the images, and quickly and accurately determines if the defects are critical or not.  Operator errors are eliminated and defect review cycle time is significantly reduced, in some instances by greater than 75 percent, according to Luminescent.

Computational defect review of this sort opens a broader field which Luminescent calls “computational lithography and inspection (CLI)”. Computational lithography uses mathematical models to improve the resolution and process window of photolithography imaging without changing the exposure wavelength by adding structures on the mask or altering exposure illumination. Computational Lithography has become the most viable and economical approach for extending optical lithography for several generations, according to Dr. Morris Kori, CEO of Luminescent.  Computational inspection integrates with computational lithography by using similar mathematical approaches to filter for photomask defects by simulating pattern errors on final silicon.

In a paper at last April’s Photomask Japan in Yokohama, C. Y. Chen of TSMC E-Beam Operations Division and a team from TSMC and Luminescent described the use of computational inspection methods to analyze the images produced by Zeiss AIMS defect review tools at TSMC’s maskmaking facilities. The AIMS tool finds defect locations flagged by a KLA-Tencor mask inspection system and determines the image that would be projected onto the wafer by that defect using optics and illumination that mimic those of the production stepper.

Matching defect and reference images automatically (source: Luminescent)

The Luminescent Automated Image Processor Hub (LAIPH, pronounced “life”), then compared the AIMS defect image to a reference image (see figure), accounting for potential tilts and misalignments and determined whether that mask site passed or failed specifications. Both contact and line/space patterns were reviewed automatically and the results correlated with manual measurement of indicated wafer CD error. The Luminescent system correlated essentially perfectly with the operator results, with the discrepancies mainly due to the operator’s inability to identify contact position shift. Throughput improvement using the automatic measurements was significant. An operator took 40 minutes to perform the X/Y measurements on 17 blind or mis-sized contact defects, while it only took LAIPH only 1 minute.

The authors noted that the TSMC EBO processes more than 167 masks per day. On average, there are tens to hundreds of defects per mask requiring AIMS review and dispositioning. The Luminescent aerial-image-based automatic mask defect disposition system evidently was able to handle this throughput resulting in acceptance at the “premier Asian facility” mentioned. –M.D.L.

At the SEMICON West 2009 Device Scaling TechXPOT, moderated by this editor, SEMATECH’s Ray Jammy reviewed the latest results in scaling CMOS transistors. “We are litererally running out of atoms,” explained Jammy. “You can see the number of atoms in a gate dielectric.” When you have such thin layers, how do you control device parameters? Metrology is also an issue; how do you see what you have made?

MOSFET scaling requires the control of the ultra-small and control. New materials are generally the solution, with more complex combinations of elements capable of providing high mobility with low leakage. Multiple gates (either dual-gate planar, or multi-gate fin)  and nanowires may provide better electrostatic control.

Jammy also discussed extensions of high-k (HK, where “high” is conventionally used to denote the modest k range of 10-20) interface engineering work needed to ensure ultra-shallow junctions for source and drain device regions. Derived from the “dipole engineering” of aluminum oxide (AlOx) for NFET and lanthanum oxide (LaOx) for PFET devices so that both can use a single metal contact, SEMATECH has been working on ways to use a “simple nitrogen-based interface” to lower the S/D contact resistance by an order of magnatude. The contact resistance is dominated by NiSix.

SEMATECH partner Mattson Technologies provides the rapid thermal processing (RTP) tooling used in the work (see figure) on gate and junction formation. Millisecond annealing is achieved by ramping the whole wafer up to a moderate temperature, and then flashing a light source for such a brief period that only the top side of the wafer is heated to a higher temperature. With proper control, this results in the bulk of the wafer being a heat sink to help rapidly cool the top side. Mattson’s RTP technology director, Paul Timans explained that different RTP approaches require different ion implant recipes to ensure optimum results. For example, changing to a millisecond anneal from a Spike anneal resulted in non-ideal Halo implant activation, such that dose and energy had to be adjusted to ensure proper device results.

For sub-30nm-node devices, preliminary data show that leakage from the gate dielectric alone is starting to dominate the power, so gate leakage must be controlled regardless of gate equivalent oxide thickness (EOT) or S/D structures.

High-k  dielectrics based on hafnium oxides that may be alloyed with Si and N are the current standard for CMOS gates <45nm node. Whether integrated in “gate-first” or “gate-last” flows, the HK layer currently sits on top of a ~1nm thick SiON interface layer (IL). The IL generally grows from the channel surface during the HK gate deposition process, such that it has conventionally been considered as an inevitable part of the structure.

A later Device Scaling TechXPOT presentation by SEMATECH director of front-end processing Paul Kirsch on HK and metal gate (MG) for 22nm node and beyond devices showed breakthrough results on ability to reduce the IL to nothing. Zero interface layer (ZIL) HK uses HfOx directly on Si  capped by MG (see figure). The TEM image shows ~10° angular misalignment between the crystalline HfO2 and the underlying Si. Somehow, the process flow ensures both ZIL and almost no interface defects.

In a private message to BetaSights, Kirsch mentioned that, “We worked pretty hard to control the Hf : O ratio during the dielectric deposition. With the ‘correct’ Hf : O ratio, we were able to keep the annealing for S/D the same (i.e. a 1020C spike). This is useful for both gate first and gate last approaches.”

SEMATECH labs are already working on HKMG over both Ge and InGasAs with ZIL. Metrology for HK is VUV reflectometry (Ref: Metrosol), where one tool provides LaOx, AlOx, HfOx, HfSiO, SiOx interface measurements.

Monolayer caps of molecules to control work function have recently been explored by researchers at Rice University and North Carolina State University (NCSU). James M. Tour (Rice) and Paul D. Franzon (NCSU) et al. published “Controllable Molecular Modulation of Conductivity in Silicon-Based Devices” (Ref: J. Am. Chem. Soc., 2009, 131 (29), pp 10023–10030), showing that a molecular monolayer, covalently grafted atop a silicon chanel, can play a role similar to gating and impurity doping.

Charge transfer occurs between the silicon and the molecules upon grafting, which can influence the surface band bending, and makes the molecules act as donors or acceptors. The partly charged end-groups of the grafted moleculular layer may act as a top gate. The doping- and gating-like effects together lead to the observed controllable modulation of conductivity in pseudometal oxide semiconductor field-effect transistors (pseudo-MOSFET). If such grafted molecules can withstand 450°C to allow for standard metal interconnect processing, then such devices could be easily mass produced in current IC fabs.

If you are interested in HKMG technology, then you definitely want to be in San Francisco during August 24-26 for the IEEE-SEMATECH 6th International Symposium on Advanced Gate Stack Technology. Top researchers from GlobalFoundries, IBM, Intel, Samsung, TI, Qualcomm, and major universities will present their findings on unit processes, integrated flows, and future devices. –E.K.

While EUV Lithography may now be inevitable, according to SEMATECH Program Manager Bryan Rice, it may not be indispensable. SEMICON West offered a snapshot of progress towards the 32nm, 22nm, and 16nm device nodes at the Device Scaling TechXPOT, and the industry appears to have patterning options even if EUV encounters further delay.

Yan Borodovsky of Intel spoke about lithography options for high volume manufacturing. For Intel, pitch splitting – PS, a generalization of double patterning – with 193nm illumination is the default option through the 16nm node. Of course, for Intel, 16nm devices are fabricated at 60nm pitch, 30% larger than industry convention. Even so, implementing high volume manufacturing at 16nm in 2013 can be done with 193nm immersion exposure tools and an infrastructure that exists today. It just will take more exposures and processing.

Beyond 16nm, the options were more difficult and uncertain. Borodovsky reported that Intel hoped to implement 11nm at 40nm pitch with pitch splitting in 2015, even though the ITRS did not call for 40nm pitch until 2017. If there were a next generation lithography tool demonstrated at that resolution then Intel would consider it, but the window for 11nm high volume manufacturing closes in 2011, Borodovsky warned. He suggested that there were 3 possible follow-on technologies: EUV, Imprint, and direct-write e-beam. None seemed likely for main-stream production, although he allowed that some new lithography technology could usefully compliment pitch splitting on low density layouts.

Borodovsky also showed a pitch quartering (P/4) approach to 7nm lines (28nm pitch) fabricated with one 193 immersion mask exposure and two steps of sidewall-spacer pitch-splitting. Thus the initial pitch was 112nm, well within current technology. Cutting such patterns into useful circuit element certainly requires more exposures and processing, but that, by definition, occurs at lower density.

Imprint
Mark Melliar-Smith, president of Molecular Imprints, Inc., predicted continued expansion of the market for imprint lithography in an exclusive BetaSights interview at SEMICON West. He sees MII’s core market as data storage, both hard disk drives and non-volatile semiconductor memory. Both have challenging resolution and cost requirements coupled with more tolerance of defects than logic/MPU lithography. Imprint has intrinsically low cost due to the simplicity of the tool and low consumption of resist, he said.

The mask issue is being addressed through a partnership between MII and DNP, the leading mask house. DNP can already make 2x generation master masks, repaired to have zero defects, but their cost is >$150,000. Soon, they will implement an imprint replica process to make much less expensive working masks for printing on wafers. With MII’s help, DNP hopes to make hundreds of replicas per master, and each replica would then print hundreds of wafers. MII’s first generation high volume single head manufacturing tool for semiconductors is scheduled for delivery in 2011, with 8nm overlay and 20 wph throughput. A cluster tool would follow in 2013.

In the hard disk drive business, MII has 11 orders with 9 tools shipped. High volume manufacturing (at 350 two-sided-disks/hour) will begin this year on the first cluster tool, at a resolution below 20nm. The disk makers themselves had taken on the task of making the replica templates for production, rather than relying on the mask industry, according to Melliar-Smith. Headcount at MII has grown to 127 and hiring continues as tool production ramps up for the magnetic and semiconductor data storage markets.

EUV Hunger
Borodovsky and others are still betting that EUV will be the follow-on technology to pitch division with 193nm water immersion exposure, but when it will happen and at what cost remains uncertain. Bryan Rice of SEMATECH reported that there still remained 3 major roadblocks: the source, line width roughness in the resists, and defectivity still 100x acceptable. While optical tools can inspect 40nm EUV masks, SEMATECH has undertaken to build 3 prototype actinic inspection prototypes. According to Rice, actinic inspection tools need to be produced commercially – and soon.

Bruno La Fontaine of Global Foundries pointed out that, while EUV wasn’t ready for high volume production, its competitors weren’t either. Thus, there were no technologies to exercise. He claimed that EUV would be cost comparable with pitch splitting for wafer runs of 5000 if the exposure tool could run at 60wph and cost the same as the DUV scanner – so long as the mask cost was in the same ball-park as DUV. He noted that only 10% of the defects found on EUV masks printed – probably a result of the higher image quality. When would EUV be ready for pilot production? La Fontaine speculated that 2014 was possible, but not certain. By then Borodwski and Intel expected to be splitting their way to 11nm, requiring NA>0.25 and RET for the EUV tools to be competitive.—M.D.L.

Evergreen Solar, the manufacturer of “String Ribbon” solar power products, announced it has finalized agreements with Jiawei Solarchina and the Wuhan government’s Hubei Science & Technology Investment Co., Ltd. (“HSTIC”) for the setup and operation of a new 100MW mc-Si panel fab. Factory construction has begun and the parties expect that wafer, cell, and panel production will begin in the spring of 2010. The parties currently intend to expand production capacity of their respective manufacturing operations to ~500MW by 2012, though the timing and extent of any potential expansion will be reset in 2010.

Evergreen Solar will manufacture String Ribbon wafers using its newest Quad furnaces (see figure) that grow four 3.2-inch (80mm) wide strips of mc-Si at a time. Long high-temperature filaments unwind from spools, run through molten silicon, and pull a long 190µm thin strip of silicon out of the melt. The wafer strip is then cut into smaller pieces for further processing into solar cells, such that just 2g/W of Si is used.

Evergreen Solar in Wuhan will be in a leased facility being built by Jiawei in Wuhan, China on Jiawei’s campus, as part of a complex set of financial arangements:
* Jiawei will convert the String Ribbon wafers into Evergreen Solar-branded panels on a contract manufacturing basis.
* Evergreen Solar will reimburse Jiawei for its cell and panel conversion costs, plus a contract manufacturing fee. The actual price paid to Jiawei will be negotiated annually.
* Evergreen Solar will invest $17 million in cash and equipment in the Wuhan String Ribbon operation. HSTIC will provide Evergreen Solar $33 million of 7.5% financing, which Evergreen Solar must repay no later than July 2014. Jiawei will make a similar investment for its cell and panel operations with the support of HSTIC.
* Evergreen Solar and Dynamic Green Energy, Ltd, Jiawei’s parent company, have agreed to exchange warrants representing 1% of their outstanding shares. These warrants will have a five-year term and may be exercised for 20% of the warrant shares for each incremental 95 MW of production capacity achieved.

“Our String Ribbon wafer technology, combined with Jiawei’s low-cost manufacturing capabilities, should enable our products to stand out distinctly among customers seeking both value and dependability for their solar energy solutions,” commented Richard M. Feldt, Chairman, President and CEO. “As we reach the 25 MW quarterly capacity by the end of 2010, we expect total manufacturing costs of our String Ribbon panels produced in China to be in the range of $1.40 per watt to $1.50 per watt with both companies working aggressively to further improve technological performance as well as reduce manufacturing costs. Our mutual goal is to drive conversion efficiency and manufacturing performance so that panels are produced at the $1.00 per watt level by no later than 2012.”

Proof of the company’s ability to deliver is in the latest financial results including news that the flagship Devens, Massachusetts fab shipped 23.2 MW of products at an average price of $2.70/W in the second quarter of 2009, which is a 34% volume improvement on the 17.4 MW sold at $3.13 in the first quarter of the year. “We continue to ramp our production at Devens in line with market demand,” stated Richard M. Feldt, Chairman, CEO and President. “The momentum we are building keeps us on track to achieve our $2.00 per watt goal when Devens reaches its 40 MW of quarterly capacity. Additionally, we are now identifying cost improvement programs that we believe will gradually take us to about $1.50 per watt at full factory capacity in the next two years.” Revenues for the second quarter of 2009 were $63.8 million, compared to $55.8 million for the first quarter of 2009, and $22.8 million for the second quarter of 2008. –E.K.

At SEMICON West and Intersolar North America last week in San Francisco, crossing guards danced to keep the throngs away from the vehicles at the corner of 4th and Howard, as many people flowed back and forth between the shows co-located across 4th Street from each other. SEMICON West, down ~30% in size from last year, still fill most of both North and South Halls in the Moscone Center. Intersolar, continues to grow and now fills most of all three levels of West Hall. Excellent technical presentation and keynote addresses, leading exhibitor booths, standards meetings, and many side events combined to make this an intense work week.

SEMICON now includes focused technical presentation sessions called “TechXpots,” and this editor moderated the first session on device scaling entited, “Advanced Processes and Materials for New Devices.” Raj Jammy, SEMATECH VP of  Materials and Emerging Technologies, provided an extremely authoritative overview of the scaling challenges and currently known solutions to get to 16-22nm node devices. He showed that new materials (like III-V and II-VI compounds) and new devices (like finFETs and quantum well devices) allow for evolutionary extensions of CMOS, and when eventually needed we may be able to lead a revolution using graphene transistors and nano-electromechanical system (NEMS) switches.

Much of the near-term CMOS processing challenge involves non-equilibrious rapid thermal processing (RTP) to be able to control atomic layers in manufacturing, as described by Paul Timmons of SEMATECH OEM partner Mattson Technologies. Many of the slides shown in TechXpots and keynotes can now be found online, and all are worth reviewing.

Humans focus on large negatives while ignoring small positives, and so we notice and remember when a big company disappears from a market, but never notice the many upstarts that grow to serve that same market. A bogus “common sense” tends to develop when people fail to check the data, and eventually myths arise in a market. In the IC fab market, it is common for people to feel and express that maturation has led to inevitable consolidation, and that new fab technologies adoption is slowing down.

These two myths were ably dispelled by Mentor Graphics Corp. Chairman Wally Rhines in his Wednesday morning keynote; download the full slide set from SEMI. Drawing on data from leading analyst houses, Rhines showed that the market share held by the top 10 IC suppliers and even the top 5 DRAM suppliers has remained nearly constant over the decades. His company’s own data on the rate of adoption of new technology nodes—as seen in design starts—seems to confirm reticle and wafer start data showing that new nodes are being used about as fast as in the past. Examples of 45nm and 32nm node IC technology opening up new end-uses to drive more IC unit volumes include CMOS image sensors, cell phone handset SoCs, and embedded software applications allowing chips to be ever more functional. Rhines observed that—unlike in past downturns—there was no fab equipment boom in recent years, so there is not supposed to be very much excess IC fab capacity in the world today.

The official data shown during the SEMICON press conference indicate that the IC fab industry has already bounced off the bottom of this cycle (see figure). This last downturn has seen many segments of the IC fab ecosystem revenues down to 2001 levels, while the last quarter has typically seen improvements up to 2005 levels. SIA/WSTS data for May 2009 show that IC unit shipments declined by 36.7% 4Q08-1Q09, which was the largest percent decline and the steepest slope of any downturn in history. SEMI’s silicon wafer area shipment data—not including PV wafers—show that fabs had rapidly cut their wafer starts over the last year. Thus, it seems that there really should be minimal IC inventory in the world, and the second half of this year should see a slow and steady increase in production.

The PV fab industry is still very immature. Investors still see it as an intellectual property (IP) land grab, and like all information flows to be one-way in. Technologists seem like teenagers; first to think of everything, and haven’t yet learned how to share well. Consequently, essentially all process information is consider novel and proprietary, so it was refreshing that some of the InterSolar North America presentations discussed fab technologies. Evergreen’s ribbon silicon pulling technology is genuinely unique and currently in mass production; yet it seems rather immature with a lot of room for improvement in both fundamental material properties as well as fab costs. Konarka Technologies has retrofitted an old Polariod factory in Massachusetts to be able to produce 1 GW of organic PV panels each year.

The immaturity of the PV industry can also be seen by wide demand swings. With demand for PV still limited by global financial insanity, and with the “overhang” inventory of some GW of modules allegedly stuck somewhere in Spain, the demand for PV fabs is anything but certain today. However, with PV currently supplying somewhere near 0.02% of global energy use—glibly characterized as a “rounding error” by one presenter—there’s nearly endless growth potential.

More details about SEMICON, InterSolar, and growth in PV, MEMS, and non-silicon semiconductor fabs will follow in future BetaBlogs. –E.K.

Intersolar North America 2009, co-located with SEMICON West in San Francisco next week, will include a Solar Startups Forum on July 16 to showcase some new technologies that are now in beta tests in the field. Select companies will make in depth presentations and offer insight into the atmosphere and environment of the solar industry from the perspective of a new company “breaking in.” Intersolar programs and events have been set to serve the diverse interests of investors, technologists, executives, government representatives, analysts and journalists, as well as those looking to get into the solar industry.

The recent U.S. Stimulus Package, intended to spur the development of the renewables sector, is sure to create plenty of interest in new business ventures. The Solar Startups Forum features presentations from companies who have recently broken into the solar industry with the aim of exchanging their experiences, obstacles encountered, and success stories with attendees.

Skyline Solar CEO Dr. Bob MacDonald will discuss the company’s patented CPV architecture. As covered in detail over at PV-Tech, Skyline Solar uses curved mirror arrays and one-axis tracking (see figure) to hit a claimed sweet spot of cost:energy-output for municipal arrays ranging from 50-100 kilowatts up through many megawatts. The company’s first installation is near it’s HQ in Silicon Valley at a Santa Clara Valley Transportation Authority bus maintenance facility.

The next level up in complexity and energy density is dual-axis tracking for 500x CPV using multi-layer-epitaxial compound semiconductor cells with efficiencies >35%. This is the technology used by Soliant Energy, and company CEO Marco DeMiroz will talk about installations on rooftops and large areas to create virtual grids for municipalities.

Chasing the world leader in CdTe is PrimeStar Solar. PrimeStar Solar is developing US NREL CdTe IP with GE money. The company has highly experienced teams working on custom thin-film deposition tooling to build it’s own line. Brian R. Murphy, PrimeStar Chairman, CEO and Founder, will talk about the company’s 60 cm x 120 cm frameless glass-glass photovoltaic (PV) module that is optimized for use in large scale grid connected installations.

Thinking big picture about materials basics, the founders and leaders of 1366 Technologies have decided that silicon is the only material that is cheap and plentiful enough to be able to make a difference in world energy. Craig Lund, Director of Business Development, 1366 Technologies, will give a talk about, “Enabling TeraWatt Photovoltaics” using multi-crystalline silicon (mc-Si) manufacturing and assembly technologies that aim to reach $1/Wp by 2012. –E.K.

Applied Materials has extended physical vapor deposition (PVD) technology to be able to coat the sidewalls of 22nm node structures. “It’s been validated, it’s been shipped, and it’s been qualified in pilot lines for both logic and memory,” asserted Marek Radko, Applied Materials’ BEOL GPM Manager, in an exclusive interview with BetaSights. Separately, the company has also launched a lower cost PVD tool targeting chip packaging lines. Based on multiple successful beta site tests for each tool, these offerings significantly broaden the company’s deposition product lines.

With >8 layers of on-chip interconnects typical for advanced ICs today, the majority of thin-film deposition tools are tied to dual-damascene copper process flows. So while the dielectrics are deposited as blanket layers, the metals must be deposited into ever smaller spaces as feature sizes continue to shrink. Electro-chemical deposition (ECD) grows the copper lines from barrier and seed layers deposited by PVD.

PVD (with variations known as “sputtering” and “evaporation”) has been used to coat metals on ICs for decades. The metal source may be a solid “target” or a liquid melt, but in either case energy is applied to vaporize the metal inside of a vacuum chamber, and metal atoms fly off to coat the surface of substrates. One of the major limitations of PVD is that the coating is “line of sight” from the source to the substrate, such that the sidewalls of features on non-planar substrates are difficult to cover. The smaller the structure, the more difficult it is for PVD to coat sidewalls.

Chemical-vapor depostion (CVD) and atomic layer depostion (ALD) technologies use chemical precursors (instead of the pure material used in PVD) that are tuned to react only on the substrate surface, so growth on sidewalls may be nearly equal to that on the top of structures. Thus, as the IC fab industry continues to shrink circuit features, CVD and ALD have been considered as the logical replacements for PVD. However, the cost-of-ownership (CoO) for these other technologies is almost always higher compared to PVD, and the chemical reactions involved may leave trace quantities of undesirable reaction byproducts in the final film. For these and other reasons, extending PVD to be able to coat smaller structures has been pursued for many years. “We’re still working on PVD extendibility,” said Gary Miner, Applied Materials’ Front End Products Group chief technology officer, in an exclusive interview with BetaSights. “At some point there will be a transistion, but it’s very hard to predict when it will switch. Through 22nm it’s still going to be PVD.”

The new “RFX” extensions to an “Endura” chamber include new controls: uniform magnet motion (UMM) behind the target, and two different RF frequencies coupled into the chamber at different points. Flux in traditional magnetron PVD has non-optimal directionality due to non-uniform target erosion which results in within-wafer variation in sidewall coverage. A new spiraling path for the magnet (driven by interlocking gears like in the old “spirograph” child’s toy) provides far more uniform target use.

A 2 MHz RF coil above the wafer induces a secondary plasma to direct ions and improve the coverage in the bottoms of nano structures. Resputtering to optimize copper sidewall coverage is controlled by 13.56 MHz RF coupled through the electro-static chuck (ESC). You can tune the resputter to optimize different recipes for structures such as dual-damascene interconnects, trenches, or through-silicon vias (TSV).

Applied Materials claims that ~10% of the company’s total PVD sales has been for Cu barrier/seed applications, represented by 490 systems delivered to fabs. The company expects to gain sales from the major shift to Cu for memory expected over the next 6 quarters. Current generation PVD tool owners can upgrade chambers in the field to include “RFX” sub-systems.

In contrast to the extremes of process control and cost needed for the smallest commercially manufactured device structures on the planet, the company’s new “Charger” tool is designed for the modest control needed at super-micron dimensions. Target applications include under bump metallization (UBM), redistribution layers, and CMOS image sensor (CIS) lines, where there is always extreme price sensitivity. The tool targets >85% avalability and throughput >30 wph, with 5000 wafers MTBPM (mean time between preventative maintenance). Multiple systems have been shipped and are in production.

The increase in MBTPM is mainly due to the company’s new “Isani” preclean chamber, using a thin plasma sheath to provide the force for an argon plasma to sputter polyimides and nitrides from the wafer surface. The sputtered material adheres to specially designed shields, where surface textures and thermal coefficients of expansion (TCE) have been tuned to allow for the thickest possible buildup before the chamber needs a PM. –E.K.

Today, Intel sponsored a history of the planar IC event at the Computer History Museum, in Mountain View, California. This, in the same week that the company pre-launches a new advertising campaign to try to position the company as “Sponsors of Tomorrow.” Based on the live event, the past was seriously wonderful. Based on these new commercials, the future will be “of a quirky, tongue-in-cheek nature,” but that may be just what the world needs right now. Gordon Moore and Jay Last, giants who stood on the shoulders of giants, gave wonderful presentations at the event about how they invented much of IC processing 50 years ago.

The planar IC has been the foundation of the modern electronics era. Discrete semiconductors had been in commercial production for a decade when, in 1959, visionaries such as Jack Kilby (TI) and Robert Noyce, Jean Hoerni, and Jay Last (all at Fairchild) created the IC.

Early Fairchild planar transistor packaged (source: Computer History Museum)

Compared to the prior art of the “mesa” transistor, Hoerni conceived of the use of grown oxide to protect the top surface. The military was the main customer for an NPN mesa transistor (where particles shorted out transistors), while oxide passivation protected the surface resulting in high reliability with improved amplification and switching characteristics. “Jean was said to have demonstrated the first planar transistor by spitting on it to prove the reliability,” said Gordon Moore. However, the fab process was very difficult, and took a full year of pilot line work. After the planar transistor was proven (see figure), it was only a matter of time before planar processes were found for other circuit elements and the IC happened. In fact, multiple independent groups in the world developed IC building blocks that were nearly identical in concept.

Establishing the planar process saved Fairchild’s business, and ushered in silicon as the main material for semiconductor electronics. However, the company first had to sell chips at a loss and make up for it in volume. Seriously. In the early 1960s, one transistor on an IC might cost $150, while a discrete cost $3. After success in selling ICs to the military, in 1964 the technologist turned business visionary Robert Noyce decided that Fairchild should drop prices below fab costs to capture the first commercial IC business. In less than a year, the company received a single order that was equal to 20% of the value of the entire commercial industry in the prior year. “He started what has become the standard for the semiconductor industry: the solution to all problems is to cut the price,” quipped Moore. “The rest, I guess, is history.”

Gordon Moore was the director of R&D at Fairchild when the planar transistor was invented. Jay Last led R&D when IC process integration first occurred in a fab, and he spoke of it as a historic inevitability, based on prior developments in science and engineering. Fairchild was trying to make products that could make money, and so they were very focused on target applications, enabling technologies, and innovations in manufacturing. “In one way, you could say that we did for Silicon Valley what Henry Ford did for Detroit,” said Last. The proof-of-concept for the planar IC required low-yield and high-cost processing, including an isolation flow that resembles today’s state-of-the-art in packaging.

The first successful planar IC made in a batch process, involved bonding the silicon wafer face-down to a quartz “handle” wafer, thinning to 75 microns, backside etch through a mask to remove all silicon down to the surface oxide (to here, this could be a through-silicon-via flow), and then a backfill of some dielectric material. Double-sided alignment was done using IR. In late 1960, a methyl-borate source allowed for an 18-hour Boron diffusion process for isolation, and by the end of 1961 the first commercial IC was for sale using bipolar transistors. The only fundamental change since has been the introduction of the MOS transistor.

Not really Ajay Bhatt (source: Youtube)

A question from the audience at the Computer History Museum was, “Can we reinvent Silicon Valley to make it an exciting place like it was in the 1950s?” Tellingly, there was complete silence from Last and Moore, and so the moderator moved on to another question.

The future of Silicon Valley will be left to marketeers, as evidenced by the “Sponsors of Tomorrow” web page. Intel hired actors to play the real Intel employees. The absurd “Rock Stars” commercial supposedly stars Ajay Bhatt (see figure, below) who was one of the inventors of the universal serial bus (USB) standard. “Several of the engineers we’re personifying confided that acting isn’t within their comfort zone,” said Sandra Lopez, Intel’s global consumer marketing manager. Poor Ajay Bhatt is thus denied his real “15-minutes-of-fame” by an actor with a bad haircut and annoying mannerisms (see figure, above).

Ajay Bhatt (source: Intel)

The ad campaign tries to convey the idea that gigantic advances of the digital age have been made possible by silicon – and the vast majority of this silicon has come from Intel. “Our image, our brand are far too powerful to just be a microprocessor when, in fact, the greatest strength of the Intel brand will always be what is still to come,” said Deborah Conrad, Intel vice president and general manager, Corporate Marketing Group. “What Intel develops today leads the path toward a better tomorrow.” Maybe a radical new silicon technology will lead the way into the future, such as a sensor-FET out of Intel Fab8 in Israel, or some optical IC out of a secret lab.

Despite the appeal of an ideal future, we have to work in the real present, and try to sell products now. Perhaps consumers will be amused by garish parodies of engineers. Perhaps a sly wink is what will move more chips. Perhaps the “Intel inside” campaign showed that you can build consumer brand equity in the IC business, and so this is just the next step in positioning. “A heavy internal campaign is already underway at Intel campuses throughout the world,” said the press release. –E.K.

Leaving California for the first time, the 12th annual IEEE International Interconnect Technology Conference (IITC) will take place in Sapporo, Japan, June 1-3. With lithographic shrinks in 2D dimensions slowing, interconnects between chips in packages and in 3D stacks will be the driver for increased density and functionality in ICs. Thus, the more than 80 technical presentations at IITC this year will show the way toward the most likely major innovations to come in the IC fab ecosystem.

SEM cross section of 15-16 nm Cu contacts post-anneal. There is no Cu diffusion through the Ru to the silicide, and no void formation. (source: IBM)

The semiconductor industry has 65nm and 45nm node chips in volume production, most using dense, non-porous, low-k dielectrics made from SiCO(H) films (k~2.7-3.0) to isolate Cu lines, Cu vias and W contact plugs. As the world’s leading IC foundry, TSMC will present an invited paper on, “Challenges of Low Effective-K Approaches for Future Cu Interconnect.” At the smallest dimensions the relatively higher resistance of W limits performance, so Cu contacts are needed. IBM Alliance researchers used Cu contact metallization with a CVD ruthenium (Ru) liner to demonstrate the world’s smallest fully-functional 22nm node 6T-SRAM. They will show the extendibility of Cu contact metallization to 15nm contacts (see figure).

The conference will continue its 12 year history of addressing issues of interest to both the development and and manufacturing communities:

• Materials and Unit Processes
• Process Integration for Logic and Memory
• Process Control / Modeling
• Reliability
• TSV and 3-D Interconnects
• Interconnect Systems
• Packaging
• Novel Materials and Concepts.

The plenary keynote presentation will be by Satoru Fujikawa, Director, R&D Strategic Semiconductor Development Center, Panasonic on “Integrated Digital AV Platform ‘UniPhier’” which is the company’s 45nm node SoC. An invited paper on chip-package integration, “Interconnection with Copper Pillar Bumps: Process and Applications,” will be presented by Choon Heung Lee, Amkor Korea Technology. Hiroshi Toyoda, the 2009 IITC Publicity chair commented, “We will be able to incorporate a wider range of participation from Asia this year. These new perspectives will benefit all participants.”

New package architectures that use fan-out and through-mold-via (TMV) interconnects, combine with flip-chip and wafer-level packaging (WLP) to create dense IC systems with unique thermal management issues. NEC and Tokyo Institute of Technology researchers will present a paper on 3D packaging technology called SMArt chip connection with Feed Through Interposer (SMAFTI). The team implemented a new die bonding process and multilayer interconnect technology to form over a thousand parallel interconnects between memory and logic dies. They characterized the interlaminar horizontal wiring by S-parameter measurement up to 40 GHz and confirmed its potential for high-speed signal transmission at over 10 Gb/s.

“The needs of the industry have demanded IITC to adapt, both in the scope and content our technical program,” said J. D. Luttmer of DRS Infrared Technologies and IITC 2009 General Conference Co-Chair. “By rotating our forum to Asia and Europe in 2011, IITC is exposing the interconnect community to a wider audience in each region. Additionally, by focusing on emerging technologies like 3D integration, we can provide our constituents with up-to-date information to guide them as they make both strategic and tactical decisions.”

In 2010, the conference will return to the U.S., to be held at Burlingame, CA. This year, some 600 scientists, engineers, exhibitors and other interconnect professionals are expected to gather in beautiful Sapporo. The conference will be preceded by a one-day Short Course on Sunday, May 31, and also will feature a product exhibition. Lunch will be provided for registered attendees each weekday, and the popular supplier seminars will be held Monday and Tuesday nights. –E.K.