Through-silicon vias (TSV) by IBM and Semtech for ADC/DSP solutions use copper and deep-trench capacitors for RF applications; IEDM 2010 papers show TSV in active chips progressing slowly.

Leaving California for the first time, the 12th annual IEEE International Interconnect Technology Conference (IITC) will take place in Sapporo, Japan, June 1-3. With lithographic shrinks in 2D dimensions slowing, interconnects between chips in packages and in 3D stacks will be the driver for increased density and functionality in ICs. Thus, the more than 80 […]

The SPIE Europe Microtechnologies For the New Millennium congress has new partners this year, with the involvement of GMM, the Society of Microelectronics, Micro and Precision Engineering and the magazine mst|news as Cooperating Organisations for the first time. The event will be held at the Congress Centre Maritim Hotel in Dresden, Germany, 4-6 May 2009. […]

The control of complex interdependencies is critical for the successful manufacturing of nanometer-scale ICs. Every aspect of every unit process step in the line must be ever more tightly controlled to ensure that 45nm and 32nm node chips can be made with good yield. To serve the market, Novellus continues to announce new integrated surface-treatment […]

Mentor Graphics has announced new capabilities to the Calibre(R) platform to allow designers to control thickness variability due to Chemical Mechanical Planarization (CMP) at advanced process nodes. Designers can transition from dummy fill to density-based fill, or to full model-based fill, depending on the demands of their designs and target manufacturing process. The new capability […]