Through-silicon vias (TSV) by IBM and Semtech for ADC/DSP solutions use copper and deep-trench capacitors for RF applications; IEDM 2010 papers show TSV in active chips progressing slowly.

Applied Materials lauches Centris platform for AdvantEdge MESA etch chambers, claiming 180 wph throughput, 0.8nm CD, and 30% lower CoO. Also releases new ultra HDP Silvia etch chamber for Centura, claiming $10 per wafer TSV etch.

Xilinx 28nm FPGA Virtex-7 uses TSMC 65nm multi-level-metal (MLM) and through-silicon-via (TSV) Si-interposer for 2M gate and ARM-core integration product family.

TSV for 3D integration of heterogeneous ICs used in interposers first, as shown at SEMICON/West, IMAPS, IEDM and companies like ASE, Alchimer, Suss, EVG, Novellus, Vertical Circuits, and IBM.

ALD/CVD systems for new materials R&D by Altatech Semiconductor sold to Fraunhofer IZM ASSID and ENAS for 3DIC and high mobility research using liquid injection of precursors.

The IEEE’s International Electron Devices Meeting (IEDM) is still the place to see the latest micro- and nano-electronics research targeting commercial markets. On December 8, 2009, French researchers from Leti/Minatec showed “3D sequential CMOS integration” as <600°C processing of PFETs using a (110) orientation FDSOI layer that was transferred on top of NFETs made using […]

IMEC/F-IZM/SUSS/TM vs. SEMATECH/Leti/EVG/Brewer. The leading R&D consortia have aligned (pun intended) with leading equipment and materials suppliers to create ultra-thin silicon wafer handling technologies for 3D ICs. With the ability to shrink circuit dimensions in 2D becoming ever more difficult, most of the world’s IC fab leaders are evaluating the use of the 3rd dimension. […]

Applied Materials has extended physical vapor deposition (PVD) technology to be able to coat the sidewalls of 22nm node structures. “It’s been validated, it’s been shipped, and it’s been qualified in pilot lines for both logic and memory,” asserted Marek Radko, Applied Materials’ BEOL GPM Manager, in an exclusive interview with BetaSights. Separately, the company […]

Leaving California for the first time, the 12th annual IEEE International Interconnect Technology Conference (IITC) will take place in Sapporo, Japan, June 1-3. With lithographic shrinks in 2D dimensions slowing, interconnects between chips in packages and in 3D stacks will be the driver for increased density and functionality in ICs. Thus, the more than 80 […]

Applied Materials and Disco announced a joint effort to develop wafer thinning processes for fabricating through-silicon vias (TSV) for future 3D IC stacks. The two companies, world leaders in thin-films and thinning (respectively) for silicon wafers, will be working together to develop integrated, high-performance process flows intended to lower the cost, reduce the risk and […]