IEDM 2010 showed evolutions of NAND Flash with ALD IPD and ECC to 1Xnm node processing, and embedded-DRAM (eDRAM) capacitor stacks in porous low-k, meaning mainstream memory technologies will continue to dominate commercial volumes.

Through-silicon vias (TSV) by IBM and Semtech for ADC/DSP solutions use copper and deep-trench capacitors for RF applications; IEDM 2010 papers show TSV in active chips progressing slowly.

Based on proven hardware sub-systems from previous models, Applied Materials has released a new chemical-mechanical planarization (CMP) tool that processes two 300mm diameter wafers simultaneously on each of two plattens. Initially targeting copper interconnect formation for memory ICs, the Reflexion GT tool has passed betasite tests at multiple customers, and reportedly provides 60% higher throughput […]

Leaving California for the first time, the 12th annual IEEE International Interconnect Technology Conference (IITC) will take place in Sapporo, Japan, June 1-3. With lithographic shrinks in 2D dimensions slowing, interconnects between chips in packages and in 3D stacks will be the driver for increased density and functionality in ICs. Thus, the more than 80 […]